Memory organization in VDC interlace?

[nikoniko]

When using an interlaced bitmap mode, how is memory organized?

Is it laid out as a linear frame, with line 0 (first field) followed by line 1 (second field), or do you have a separate block for the first field, line 0,2,4,6, etc., followed by a block for the second field, lines 1,3,5,7, etc?

[nikoniko]

Just in case anyone else was wondering, the answer is #2: the two fields are (unsurprisingly) separate, with the even field as the first block.

[hydrophilic]

It sounds like you got a C128 to experiment with again!

Since interlace requires twice the storage (assuming sync+video mode), that means a flat C128 with only 16K VDC RAM would be unable to use this 'high def' bitmap mode... unless the VDC is switched to 'double pixel width mode' (and then still no memory for color).  Kinda of an unique idea since this means swapping horizontal resolution for vertical resolution.

If I understand you correctly, the memory is laid out in two seperate bitmaps for even and odd lines (fields) which is very similar to my VIC interlace mode -- even more similar if 'double pixel width' mode is used.  Sounds like an opportunity for a dual-monitor interlaced program.

[nikoniko]

Nope, still without 128. Just took a closer look at some Fred Bowen code which uses interlace and found the answer. I suppose they didn't put the info in the PRG or Mapping the 128 since 1) Interlace is pretty impractical with the 16K VDC, unless you're doing double-pixel or otherwise reduce your number of rows and columns, and 2) Having two separate fields is the easy and obvious way to design the hardware. I just didn't want to make assumptions.

Sounds like an opportunity for a dual-monitor interlaced program.

That would be very cool, albeit headache-inducing.