Tricks to speeding up overall VDC display speed

[Blacklord]

Tricks to speeding up overall VDC display speed:

- Reduce the high byte of the dram refresh rate (reg 36) to zero (there
  is still a hard coded low byte of the refresh rate).  It
  results in a 20% overall speed increase.  This increase can be
  seen in ready mode.  List a long basic program and time it -
  then set the HB of the vdc refresh rate to zero and list the
  program again - instant bolt on speed improvement.

- Reduce the number of visible columns to around 60.  Another 20%.

- Reduce the number of visible rows. (major increase).

The above 3 suggestions hold true for both text and graphics modes.

[Douglas]

Tricks to speeding up overall VDC display speed:

- Reduce the high byte of the dram refresh rate (reg 36) to zero (there
  is still a hard coded low byte of the refresh rate). .

Is this something that can be done using a poke from basic, or is it from machine language?

Sorry for the ignorance.

Douglas

[nikoniko]

Yep. There's a kernal routine at $CDCC which handles writing to VDC registers. You can call it from BASIC with

SYS DEC("CDCC"), value to write, register to write to.

[Douglas]

Yep. There's a kernal routine at $CDCC which handles writing to VDC registers. You can call it from BASIC with

SYS DEC("CDCC"), value to write, register to write to.

Cool...so in your basic program you would add a line like this??...

10  sys dec("cdcc"),0,36

..is that correct?

And this would speed up any basic program without any illl effects?

Cool!!!

Douglas

[nikoniko]

Even at 0, RAM should still be refreshed often enough to avoid any problems, so that would speed up any program which uses the 80-column screen a lot. Just in case of a buggy VDC, though, you could always offer a "safe mode" option which leaves the refresh alone or uses a higher value.

[nikoniko]

By the way, the opposite of the $CDCC routine is $CDDA. So when you want to read from a VDC register,

SYS DEC("CDDA"),, register to read: RREG A

The routine returns the value in the Accumulator, which we read with the RREG command. The variable name after RREG can be anything, it doesn't have to be A.

[BigDumbDinosaur]

By the way, the opposite of the $CDCC routine is $CDDA. So when you want to read from a VDC register,

SYS DEC("CDDA"),, register to read: RREG A

Ahem.  That should be BANK 15:SYS DEC("CDDA"),, register to read: RREG A

If a previous BANK command was BANK 0 or BANK 1, the screen editor ROM will be mapped out when the SYS is executed and you will find yourself pressing the reset button.

[nikoniko]

Thank you for the correcting my omission! Although bank 15 will often be in effect when working with BASIC, you're right that it shouldn't be assumed.

[BigDumbDinosaur]

Here's one more trick which actually has nothing to do with the VDC per se:

Code Select Expand

lda #%00001110
sta $ff00
lda $d030
ora #%00000011
sta $d030
To reverse the process:

Code Select Expand

lda #%00001110
sta $ff00
lda $d030
and #%11111100
sta $d030
Simultaneously setting bits 0 and 1 in the VIC's clock rate register not only sets the system clock to 2 MHz, it tells the VIC to stop accessing the address and data lines (40 colume display will also go blank).  The result is that the 8502 gets all available bus time and processing is slightly speeded up over merely using FAST mode.

Note that the processor clock rate has absolutely no effect on hardware access anywhere in the $D000-$DFFF range.  That range is controlled by a separate I/O clock that always runs at about 1 MHz.