RTC for the C128

[Mark Smith]

Hiya,

Can someone point out to me why this can't be put into the option ROM socket and provide a real time clock ?

http://focus.ti.com/docs/prod/folders/print/bq4830y.html

Might even be able to load the 32K of RAM with the routines required to use it.

Though I'm thinking setting the time would be awkward ... can you write to the ROM socket ?  Even though a ROM would normaly resist such things, is it still possible to send a write to those addresses ?

Just idle thoughts :-)

Mark

[megabit]

You would have to make an adapter to mount it on and add circuitry for read/write control.

Dan...

[Mark Smith]

But for reading the time you would need to do nothing, surely it would just be a case of reading the time out (as the part has 32,760bytes of RAM and then the last 8 bytes are the clock).

Mark

[megabit]

1.  The device comes from the factory with the oscillator off to conserve the battery. From the data sheet:

"OSC set to 1 stops the clock oscillator. When OSC is reset to 0, the clock oscillator is turned on and clock updates to user-accessible memory locations occur within one second. The OSC bit is set to 1 when shipped from the Benchmarq factory."

2.  Then the date and time will have to be set. From the data sheet:

"Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. Use the write bit, D7, only when updating the time registers (7FFF–7FF9).

3.  Then you can read the date and time. But, from the data sheet:

"To prevent reading data in transition, updates to the bq4830Y clock registers should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the read bit should be reset to 0 in order to allow updates to occur from the internal counters."

You have to be able to control CE, WE and OE.

[BigDumbDinosaur]

The TI RTC is very similar to the Dallas 1216E SmartWatch.  In either case, you have to be able to do writes to the ROM socket's address space when it's mapped in.  I haven't exhaustively studied the 128's circuitry, so I'm not sure if a R/W line is wired to the socket.  If not, a mod to provide that function probably wouldn't be too difficult to accomplish.  This is conjecture on my part, since I don't have any 128 hardware to examine.

[Mangelore]

Hi guys,

Unfortunately, the Function ROM socket does not include a R/W line.  The other issue is that the PLA won't permit writes to the Function ROM socket. When the MMU sets MS0 to Low and MS1 to high, the Function ROM is selcted. However, when R/W is LOW the PLA ignores the state of MS0=0 and MS1=1 and the writes are written to system RAM.

Cheers,
Fotios

[SmallCleverDinosaur]

This issue has been up in other threads. As you may remember Twin Cities published an article in issue #32 covering the possibility to put a static RAM in the empty socket of the C128. Someone was kind enough to post a scan of that article here in the forum. I've taken the liberty to somewhat "clean it up" by OCR'ing it. So now it's searchable and much more readable Get it here.

I've also taken the Basicloader and the ML assembler-code that was in the pdf and put it in a D64, here.

Hope it will be of use to someone

Mark, I suspect it could be used with the NVSRAM you linked to, since the pin-layout of that circuit is most likely the same as for example SRAM 62256.