C-128 Z80 phi - visualized with analyzer.

[XmikeX]

Zer0-X from Finland (kiitos!) was kind enough to test the 4 MHz clock on z80's pin 6 with his analyzer.
He generated the .gif attached to this post.

XmX


EDIT : okok.. i'm hearing from non-registered users that they can't see the attachment.
           Here's a link to the file: http://starbase.globalpc.net/~xmx/z80phi.gif  (temporary, may expire)

[Hydrophilic]

Pretty cool.  Looks just like I would expect.  Much more interesting would be a comparison of signals.  In particular the data latch/gate in relation to Z80 clock.  Also comparison of AEC and 2MHz with Z80 clock would be interesting.  Of course that would be a bit trickier to capture.

[XmikeX]

This next recording from Zer0-X, attached below, is synced to z80phi.

http://starbase.globalpc.net/~xmx/C128_Z80_boot.gif  (temporary link)

XmX

[XmikeX]

For reference, Zer0-X is using a Zeroplus Logic Cube LAP-C 16032 that has been modded to 322000 model by changing the internal SRAM chip and soldering in another bus transceiver and other required components.

Pic below:

http://starbase.globalpc.net/~xmx/zrx_zeroplus.jpg (temp link)

XmX

[StyleCHM]

Mike, any chance you can ask Zrx to do this again but flip fast mode on?

[Hydrophilic]

Wow, that's a much more interesting capture.  But even at full size, I can't quite make out the 4MHz clock.  If the time window were about half that size it should be possible. 

What is surprising is how little activity there is on /BUSRQST and /BUSACK... I'm guessing cuz they're only used to switch off the Z80 for the 8502 to take control.

The /RD and /WR lines are part of the input to the data latch/gate circuit, so that's a good start.  I don't think /RES, /IRQ, and /M0 are very useful.

The /WR line goes through several logic gates and eventually an unamed signal (from U31 pin 11) goes to gate the data on pins 1 and 19 of U13.  That is probably better to use than /WR.

The /RD line is used along with D1MHz as inputs to the data latch (pins 1 and 11, respectively, of U12).  D1MHz is also available at pins 3 and 10 of U56 (it is just a slightly delayed version of the 1MHz signal, which should closely follow AEC).  Anyway, I think you would need both /RD and D1MHz in relation to 4MHz to figure out the read timing.

Thanks for the photo.  What a mess, but at least he's getting some interesting data.